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Multicore

The assignment of task and CPU core is displayed in the Task Configuration object on the Tab: Task Groups tab.

More and more of today's controllers have processors with multiple CPU cores.

If CODESYS is executed on a multicore controller without using the multicore feature, then the distribution of tasks is handled by the scheduler of the operating system. This is true provided that an application is executed with multiple tasks. In this case, you have no direct influence over the distribution of tasks. Depending on the load balancing, the tasks can also run on different CPU cores.

With the CODESYS Multicore feature, the IEC tasks themselves can be assigned to dedicated CPU cores, taking the acquired number of CPU cores into account. This can result in improved performance. The IEC program should be split into several tasks for this purpose.

There are two basic different strategies in CODESYS for distributing IEC tasks over CPU cores:

  • IEC task which is linked and fixed to a CPU core:

    The task is always executed on this specific CPU core. Multiple tasks can be linked to a CPU core by grouping. This is useful, for example, if the IEC program is not yet able to run on multiple CPU cores simultaneously.

  • The IEC task is executed on all CPU cores:

    The operating system takes control of distributing one or more tasks of a group on the CPU cores.

Important

When the IEC tasks are distributed over CPU cores, some changes result in the behavior in the IEC program, which have to be considered.

  • The processing of IEC tasks by priority is no longer a given. They are processed by priority only if the tasks are bundled together to one CPU core.

  • The cycle consistency of the data in the IEC task with the highest priority is no longer a given. Therefore, the data has to be copied locally at the beginning of the IEC task cycle if the values should not change during the cycle.

  • For all tasks, there is a shared process image from which the tasks operate. The ReadInputs() function is called at the start of each task and the WriteOutputs() function is called at the end. As a result, the IPO model applies for each task individually. These functions read and write to the shared process image. The process image is also physically written and the packets transmitted only when the bus cycle task is called. However, the bus cycle task waits for each call of WriteOutputs and ReadInputs of the tasks. This ensures the data consistency within the bus cycle task.

    • Outputs can be assigned only to one task.

    • Inputs can be assigned to multiple tasks, but direct access should be avoided. The inputs have to be written to local variables of the task by means of atomic operations.

    • A second task, which updates the process image with ReadInputs() in parallel to the first task, also updates the inputs of the first task while it is running.

    • As a result, the data consistency of a task is ensured only on single cores for the highest priority task.

    Tip

    You can set the bus cycle task on the PLC Settings tab.

    You can display the I/O access on the Tab: Task Deployment tab.

    For more information, see: Bus Cycle Task

  • For consistent counters (incrementer, decrementer), the atomic external library function SysCpuAtomicAdd() should always be used (for more details, see SysCpuHandling.library).

Important

Data consistency

  • Bit access (data type BIT) is not processed consistently (atomically) on multicore CPUs in the IEC program. For this we recommend that you use the external library function SysCpuTestAndSetBit(). (For details, see: SysCpuHandling.library)

  • Simple data types up to a width of 32 bits (BOOL, BYTE, WORD/INT, DWORD/DINT, etc.) are processed consistently (atomically) in the IEC program on multicore CPUs as well.

  • Data types with 64 bits (LINT, LWORD, and LREAL) are processed consistently (atomically) in the IEC program on 64-bit systems and multicore systems only. To do this, you do not need to take any precautions.

  • To access complex data types (STRING, FB, STRUCT, and ARRAY), you need to make arrangements yourself for the synchronization/consistency.

  • In the task configuration, on the Variable Usage tab, you can define whether a variable in an IEC task has read or write access.

  • On multicore systems, a "memory reordering effect" can occur. For more information, see: IEC Operator: __MemoryBarrier().

Distributing tasks over multiple processor cores

Requirement: At least two tasks are defined in your application, for example MainTask (IEC-Task) and LowTask (IEC-Task).

  1. Open the Task Configuration object in the editor.

  2. Switch to the Task Groups tab.

    The overview shows the default IEC-Tasks task group.

  3. Click Add Group to add a new task group.

    The NewGroup group is added.

  4. Double-click the group name NewGroup and change it to LowGroup.

  5. In Core, select an assignment (example 1).

  6. Open the task LowTask (IEC-Task) in the editor.

  7. In Task Group, select the new group LowGroup.

    The LowTask task is processed now by processor core 1 due to its group membership in LowGroup.

Displaying the processor load per processor core in the trace

In CODESYS, you can display in a visualization the processor load in a DeviceTrace object.

For more information on how device traces are displayed in the project, see: Accessing All Traces on the Controller

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